1. Field of the Invention
The present invention relates to logic differential amplifier circuits, and more particularly to such receivers incorporating fail-safe circuitry.
2. Background Information
Fail safe differential amplifiers or receivers provide a known output when an indeterminant or invalid input signal is present at the inputs. An invalid input signal generally occurs when the inputs are floating or three-stated, or shorted. But partial shorts or opens may lead to invalid input signals. In the face of such invalid input signals the receivers usually will oscillate, switch on noise or will be in an indeterminant state.
Prior solutions have provided bias resistors at the inputs of the differential receiver to bias the inputs to a known condition by providing a de offset at the inputs. But, such an offset may unbalance return currents, distort the output and possibly load and reduce the input signal amplitude. Other solutions have biased the inputs of the receiver to Vcc with logic to drive the receiver output to some known state.
Another solution is found in Texas Instruments differential receiver, part no. SN65LVDT32B, and several other similar devices. The circuit of this device provides two active circuit high impedance comparators sharing the receiver inputs. These comparators provide a window with one comparator providing a +80 millivolt threshold and the other a xe2x88x9280 millivolt threshold. A fail-safe timer is xe2x80x9candedxe2x80x9d with the comparator outputs and if the differential input is within the +/xe2x88x9280 millivolt window at the end of the timer period, the output is driven to a known fail safe high state. One limitation of this circuit is that the fail safe timer must switch to start the time period. If the input to the receiver is valid, say more than +80 millivolts differential, but then reverts to an invalid state, say +10 millivolts differential, the timer may not be started since the receiver output may not switch.
Another fail safe device is produced by Maxim, part no. MAX9153/4. This device is labeled as a repeater, but in fact is a differential amplifier or receiver circuit. This circuit has diode spike suppressors and may not operate when powered up with the transmission line shorted, or with low level (under 100 millivolt) attenuated differential signals. High frequencies operation may be also impaired.
The objective of this invention is to provide an active failsafe circuit that takes the output of the receiver to a known state if any of the following is true.
1. Input differential signal attenuates below a defined threshold.
2. Input differential signal collapse to 0Volt (cable shorted, line shorted, wire shorted, etc.)
3. Input differential signal goes to an un-driven, un-known state or floating inputs. (cable open, device not connected to system, etc.)
It is another objective of the present invention to provide an active fail safe circuit receiver that does not load or degrade the input signal or degrade the balance, or the dynamic range or quality of the input or output of the receiver. It is another objective to provide a fail safe receiver that operates over the entire input common-mode range and assures a known output state in the presence of common mode noise, dc bias and/or system ground offsets. It is another objective of the present invention to not affect the high frequency performance of the receiver.
It will be appreciated by those skilled in the art that although the following Detailed Description will proceed with reference being made to illustrative embodiments, the drawings, and methods of use, the present invention is not intended to be limited to these embodiments and methods of use. Rather, the present invention is of broad scope and is intended to be defined as only set forth in the accompanying claims.
The foregoing objects are met in a failsafe circuit for a differential amplifier/receivers that employs offset auxiliary amplifiers that measure the amplitude of the input differential (Vid) signal to an offset voltage, and also to measure if the frequency component of the Vid is less than a frequency limit. A separate frequency detector measures the frequency of the Vid, and a logic circuit accepts signals from the auxiliary amplifiers and the frequency detector. If the amplitude of the Vid is less than the offset voltage and the frequency is less than the limit a fail safe condition exists and the output is forced to a given state that does not follow the Vid signal. If the amplitude is greater than offset voltage or the frequency is greater than the frequency limit, the fail safe circuit is inactive and the output follows the Vid. In a preferred embodiment a time delay and an initialization circuit are implemented. In a preferred embodiment a startup circuit, a memory element and delay element and some logic elements are used for control.